Description
CH2011 is a USB compliant eUSB2 to USB 2.0 repeater supporting both device & host modes. The device supports USB low-speed (LS), full-speed (FS) and high-speed (HS) signals. The device has I2C interface which permits additional flexibility for fine tuning of
device RX equalization and TX amplitude, slew rate and pre-emphasis to pass electrical compliance tests and compensate for channel loss. The repeater application is as figure can be used at host side or device side.
Features
General System Features
— USB 2.0 and eUSB2 (rev 1.2) compliant
— High-speed, full-speed, low-speed signaling
— Host and device mode (dual-role) support
— I2C slave for registers configurations
— eUSB2 1.0V or 1.2V signaling interface
— Strap-pin options for USB 2.0 high-speed channel compensation settings
— I2C accessible debug capabilities
— Built-in 3.3V to 1.2V regulator for core power
— Package is QFN-12 (2x2mm)
What can eUSB2 do?
eUSB2 can enable smaller, more power-efficient SoCs, in turn enabling process nodes to continue to scale while increasing performance in applications such as smartphones, tablets and notebooks. eUSB2 also can support onboard interdevice connectivity through direct connections as well as exposed connector interfaces through an eUSB2 Dual Repeater.
Why should IcSpring design and develop this new chip of eUSB2?
1: eUSB2 is a good fit for device-to-device communications with smaller I/O voltages, as the system power is greatly reduced.
2: Using cutting-edge SoCs with 5-nm process nodes and beyond, while continuing to benefit from the simplicity, ease of design and omnipresence of the USB 2.0 interface.
3: More important, eUSB2 is a supplement to the USB 2.0 specification that addresses issues related to interface controller integration with advanced systemon-chip (SoC) process nodes by enabling USB 2.0 interfaces to operate at I/Ovoltages of 1 V or 1.2 V instead of 3.3 V.
eUSB2 Dual Repeater Operation
The following example block diagrams of a host repeater and a peripheral repeater with their respective host and peripheral eUSB2 port and controller. Note that the eUSB2 port and the repeater may be implemented as dual-role capable.
Differences between USB 2.0 and eUSB2
When process nodes reach 7 nm, quantum effects begin impacting high-signalingvoltage inputs/outputs (I/Os) such as 3.3 V and can no longer be easily supported. Many device-to-device interfaces already support low signaling voltages, but USB 2.0 still requires a 3.3-V I/O voltage to operate.
While USB 2.0 can continue to be integrated into SoCs with process nodes 7 nmand above, eUSB2 is a good fit for SoCs when process nodes are 5 nm and below. eUSB2 can also be integrated into other devices, also shown in the following chart of eUSB2.0 Dual Repeater Simplified Schematic, to easily interconnect with SoCs as a device-to-device interface. USB 2.0 will continue serving as the standard connector interface.
As process nodes approach 5 nm, the manufacturing cost to maintain USB 2.0 3.3-V I/O signaling has grown exponentially. eUSB2 addresses the I/O voltage gap as a physical layer supplement to the USB 2.0 specification so that designers can integrate the eUSB2 interface at the device level while leveraging and reusing the USB 2.0 interface at the system level.
eUSB2 allows significant I/O power reduction and improves power efficiency, while enabling process nodes to continue to scale. The following list shows the feature differences between USB 2.0 and eUSB2.
eUSB2 Applications
• Notebooks and desktops • Cell phones • Tablets • Wearables • Portable electronics
Others eUSB2 PHY Developing
1: eUSB2 PHY and Power Management
A conceptual eUSB2 PHY state machine is shown in following chart. It summarizes the basic behavior of the eUSB2 native operation during power-up, Connect, Reset, Resume and and Remote Wake. The state machine and native mode operation are described in detail in this section. Note that the state machine only describes the state transitions under normal operating conditions. Error situations may exist. It is implementation’s responsibility to dealwith potential error conditions in each state. It is recommended that eDSPn and eUSPn issue Port Reset to recover from these error conditions.
2:eUSB2 PHY and ISP（Image signal processing）
The Chip of eUSB2 PHY and ISP will be a eUSB2 compliant camera controller designed for laptop and desktop PCs. The built-in extreme low-power transceiver provides the superior compatibility with eUSB2+USB2 host and the best quality for image applications. It will be fully compliant with eUSB2+USB2 Video Class, properly works with native driver provided in Windows 10, Windows 11 and Windows others system. The Chip of eUSB2 PHY and ISP will integrate eUSB2+USB2 transceiver that is optimized for high performance data transfer rate, high speed MCU (Micro Processor Unit), DC-to-DC regulators, sensor controller, image signal processing engine, MJPEG compression into a single chip. It can support most available CMOS sensors from VGA (640x480) to 16 Mega pixel (4640x3480) resolution. The Chip of eUSB2 PHY and ISP will be designed to have MIPI CSI-2 four lane data interface to achieve the CMOS image sensors, it reserves the good compatible flexibilities to support more image sensors provided from various sensor vendors. ISP (Image Signal Processing) engine supports most of UVC defined image adjustments (detail descriptions are listed in followingsection). In addition, this ISP engine also has practical functions like as Lens Shading Correction, dead pixel cancellation, G1G2 filter, Color Correction Matrix, histogram statistic Auto White Balance, Auto Exposure, Auto Focus, Scaling function, Noise reduction, Filtering, Cleaning up, HDR and so on. These functions are very useful to compensate intrinsic inaccuracy in lens and image sensor to get better image quality. The inside scaling filter can scale down higher resolution to lower one for reducing size purpose.
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